Two-Bit Messages are Sufficient to Implement Atomic Read/Write Registers in Crash-prone Systems

TL;DR

This paper introduces an optimal algorithm for implementing atomic read/write registers in crash-prone systems, using only two bits of control information per message, which is a significant efficiency improvement.

Contribution

It presents the first algorithm with minimal control information size, using only two bits, for atomic register implementation in crash-prone asynchronous message-passing systems.

Findings

Uses only four message types for implementation.

Messages of two types carry data, others carry no value.

Achieves optimal control information size and improves time complexity.

Abstract

Atomic registers are certainly the most basic objects of computing science. Their implementation on top of an n-process asynchronous message-passing system has received a lot of attention. It has been shown that t \textless{} n/2 (where t is the maximal number of processes that may crash) is a necessary and sufficient requirement to build an atomic register on top of a crash-prone asynchronous message-passing system. Considering such a context, this paper presents an algorithm which implements a single-writer multi-reader atomic register with four message types only, and where no message needs to carry control information in addition to its type. Hence, two bits are sufficient to capture all the control information carried by all the implementation messages. Moreover, the messages of two types need to carry a data value while the messages of the two other types carry no value at all. As far as we know, this algorithm is the first with such an optimality property on the size of control information carried by messages. It is also particularly efficient from a time complexity point of view.