Effect of Data Sharing on Private Cache Design in Chip Multiprocessors

TL;DR

This paper investigates how data sharing affects private cache miss rates in chip multiprocessors, revealing that shared data causes a compulsory miss component that impacts cache sizing and performance optimization strategies.

Contribution

It introduces the concept of a compulsory miss component due to data sharing and analyzes its impact on cache design and performance in CMPs.

Findings

Shared data causes a compulsory miss component in private caches.

Smaller private caches can achieve peak performance in highly shared workloads.

Reallocating resources from private cache to cores can improve performance or reduce area/power without loss.

Abstract

In multithreaded applications with high degree of data sharing, the miss rate of private cache is shown to exhibit a compulsory miss component. It manifests because at least some of the shared data originates from other cores and can only be accessed in a shared cache. The compulsory component does not change with the private cache size, causing its miss rate to diminish slower as the cache size grows. As a result, the peak performance of a Chip Multiprocessor (CMP) for workloads with high degree of data sharing is achieved with a smaller private cache, compared to workloads with no data sharing. The CMP performance can be improved by reassigning some of the constrained area or power resource from private cache to core. Alternatively, the area or power budget of a CMP can be reduced without a performance hit.