Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism
Kevin K. Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert,, Mike O'Connor, Srilatha Manne, Lisa Hsu, Lavanya Subramanian, Onur Mutlu

TL;DR
This paper introduces CRUNCH, a hardware data remapping scheme based on consistent hashing, enabling efficient, low-latency dynamic resizing of large DRAM caches to save power without performance loss.
Contribution
The paper presents CRUNCH, a novel hardware consistent hashing mechanism that allows load-balanced, low-latency remapping for dynamic DRAM cache resizing, improving energy efficiency.
Findings
CRUNCH achieves balanced data remapping with low transition latency.
It enables dynamic cache resizing with minimal performance impact.
CRUNCH reduces power consumption by enabling efficient cache size adjustments.
Abstract
Die-stacked DRAM has been proposed for use as a large, high-bandwidth, last-level cache with hundreds or thousands of megabytes of capacity. Not all workloads (or phases) can productively utilize this much cache space, however. Unfortunately, the unused (or under-used) cache continues to consume power due to leakage in the peripheral circuitry and periodic DRAM refresh. Dynamically adjusting the available DRAM cache capacity could largely eliminate this energy overhead. However, the current proposed DRAM cache organization introduces new challenges for dynamic cache resizing. The organization differs from a conventional SRAM cache organization because it places entire cache sets and their tags within a single bank to reduce on-chip area and power overhead. Hence, resizing a DRAM cache requires remapping sets from the powered-down banks to active banks. In this paper, we propose CRUNCH…
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Taxonomy
TopicsCaching and Content Delivery · Parallel Computing and Optimization Techniques · Network Packet Processing and Optimization
