Simulations of a silicon pixel based on MOS Deep Trapping Gate Principle
Nicolas T. Fourches (CEA Saclay, IRFU, SEDI 91191, Gif/Yvette, France), and Wilfried Vervisch (Aix-Marseille Universite CNRS, IM2NP, UMR 7334 13397,, Marseille, France)

TL;DR
This paper presents simulations of a silicon pixel detector based on the MOS Deep Trapping Gate principle, exploring its response to minimum ionizing particles and the effects of design parameters using quantum simulation tools.
Contribution
It provides a quantitative analysis of a silicon pixel detector with a Ge-based buried gate, including parameter effects and a proposed fabrication process, advancing the development of radiation-hard particle detectors.
Findings
Measurable signal for minimum-ionizing particles within limited silicon thickness
Parameter variations like pixel thickness and size influence detector operation
Proposed fabrication techniques include deep impurity implantation and epitaxial growth
Abstract
The concept of the deep trapping gate device was introduced fairly recently on the basis of technological and transport simulations currently used in the field of classical electron devices. The concept of a buried gate containing localized deep level centers for holes (Deep Trapping Gate or DTG) renders possible the operation of this field effect pixel detector. One alternative to Deep Level introduction is the use of a quantum box, which is a hole quantum-well and an electron barrier. In all of these cases the buried gate modulates the drain-source current. This principle was formerly evaluated with realistic simulations parameters and this shows that a measurable signal is obtained for an energy deposition of a minimum-ionizing particle within a limited silicon thickness. In this work a quantitative study of the response of such a pixel to Minimum Ionizing Particles. The influence of…
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Taxonomy
TopicsParticle Detector Development and Performance · Advancements in Semiconductor Devices and Circuit Design · CCD and CMOS Imaging Sensors
