Reversible Logic Circuit Complexity Analysis via Functional Decomposition

TL;DR

This paper investigates the complexity of reversible logic circuits, connecting it with Boolean function analysis, and examines whether relaxing ancilla bits can improve upper bounds on gate count, concluding it does not.

Contribution

It establishes a theoretical link between reversible circuit complexity and Boolean function multiplicative complexity, analyzing the impact of ancilla relaxation on upper bounds.

Findings

Ancilla-free synthesis remains optimal for fewer than 8 variables.

Relaxing ancilla does not tighten the upper bounds.

Theoretical bounds are consistent with existing synthesis methods.

Abstract

Reversible computation is gaining increasing relevance in the context of several post-CMOS technologies, the most prominent of those being Quantum computing. One of the key theoretical problem pertaining to reversible logic synthesis is the upper bound of the gate count. Compared to the known bounds, the results obtained by optimal synthesis methods are significantly less. In this paper, we connect this problem with the multiplicative complexity analysis of classical Boolean functions. We explore the possibility of relaxing the ancilla and if that approach makes the upper bound tighter. Our results are negative. The ancilla-free synthesis methods by using transformations and by starting from an Exclusive Sum-of-Product (ESOP) formulation remain, theoretically, the synthesis methods for achieving least gate count for the cases where the number of variables $n$ is $< 8$ and otherwise, respectively.