Convex Optimization of Real Time SoC

TL;DR

This paper demonstrates how convex optimization can efficiently optimize real-time system-on-chip designs, significantly reducing power consumption and guiding architectural decisions in early design stages.

Contribution

It introduces a convex optimization framework for real-time SoC design, showing its effectiveness in power reduction and design exploration compared to traditional methods.

Findings

Power optimization achieves 2.5x power savings.

Convex optimization guides early-stage design choices.

Efficiently handles physical resource constraints.

Abstract

Convex optimization methods are employed to optimize a real-time (RT) system-on-chip (SoC) under a variety of physical resource-driven constraints, demonstrated on an industry MPEG2 encoder SoC. The power optimization is compared to conventional performance-optimization framework, showing a factor of two and a half saving in power. Convex optimization is shown to be very efficient in a high-level early stage design exploration, guiding computer architects as to the choice of area, voltage, and frequency of the individual components of the Chip Multiprocessor (CMP).