Tiered-Latency DRAM (TL-DRAM)

TL;DR

Tiered-Latency DRAM (TL-DRAM) introduces a heterogenous DRAM design with a low-latency near segment to improve performance and energy efficiency, enabling new caching and memory management strategies.

Contribution

The paper proposes a novel heterogenous DRAM architecture with segmented bitlines to reduce latency and energy use, and demonstrates its benefits through evaluation.

Findings

Significant performance improvements with near segment usage.

Energy efficiency gains in memory operations.

Effective hardware and software caching strategies.

Abstract

This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA 2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical problem in modern memory systems. To this end, TL-DRAM introduces heterogeneity into the design of a DRAM subarray by segmenting the bitlines, thereby creating a low-latency, low-energy, low-capacity portion in the subarray (called the near segment), which is close to the sense amplifiers, and a high-latency, high-energy, high-capacity portion, which is farther away from the sense amplifiers. Thus, DRAM becomes heterogeneous with a small portion having lower latency and a large portion having higher latency. Various techniques can be employed to take advantage of the low-latency near segment and this new heterogeneous DRAM substrate, including hardware-based caching and software based caching and memory allocation of frequently used data in the near segment. Evaluations with simple such techniques show significant performance and energy-efficiency benefits.