Time-Efficient Read/Write Register in Crash-prone Asynchronous Message-Passing Systems

TL;DR

This paper introduces a new asynchronous algorithm for implementing atomic registers in crash-prone message-passing systems, achieving time-efficient read and write operations under different synchrony assumptions.

Contribution

It presents a novel time-efficient atomic register algorithm that closely follows ABD, optimized for crash-prone asynchronous message-passing systems with minimal operation delays.

Findings

Write operations cost one round-trip delay.

Read operations cost one round-trip delay in favorable cases.

Algorithm works under different synchrony assumptions.

Abstract

The atomic register is certainly the most basic object of computing science. Its implementation on top of an n-process asynchronous message-passing system has received a lot of attention. It has been shown that t \textless{} n/2 (where t is the maximal number of processes that may crash) is a necessary and sufficient requirement to build an atomic register on top of a crash-prone asynchronous message-passing system. Considering such a context, this paper visits the notion of a fast implementation of an atomic register, and presents a new time-efficient asynchronous algorithm. Its time-efficiency is measured according to two different underlying synchrony assumptions. Whatever this assumption, a write operation always costs a round-trip delay, while a read operation costs always a round-trip delay in favorable circumstances (intuitively, when it is not concurrent with a write). When designing this algorithm, the design spirit was to be as close as possible to the one of the famous ABD algorithm (proposed by Attiya, Bar-Noy, and Dolev).