Configurable memory systems for embedded many-core processors

TL;DR

This paper demonstrates that reconfigurable memory systems in embedded many-core processors significantly improve performance and energy efficiency over fixed designs, especially under resource constraints and specific workloads.

Contribution

It introduces a reconfigurable cache architecture that outperforms fixed configurations and showcases its benefits through a case study on AES encryption.

Findings

Reconfigurable cache systems outperform fixed ones by up to 70% in performance.

Reconfigurable caches reduce miss rates by up to 90%.

Custom memory configurations nearly double AES performance.

Abstract

The memory system of a modern embedded processor consumes a large fraction of total system energy. We explore a range of different configuration options and show that a reconfigurable design can make better use of the resources available to it than any fixed implementation, and provide large improvements in both performance and energy consumption. Reconfigurability becomes increasingly useful as resources become more constrained, so is particularly relevant in the embedded space. For an optimised architectural configuration, we show that a configurable cache system performs an average of 20% (maximum 70%) better than the best fixed implementation when two programs are competing for the same resources, and reduces cache miss rate by an average of 70% (maximum 90%). We then present a case study of AES encryption and decryption, and find that a custom memory configuration can almost double performance, with further benefits being achieved by specialising the task of each core when parallelising the program.