High Current Density Vertical Tunneling Transistors from Graphene/Highly-Doped Silicon Heterostructures

TL;DR

This paper demonstrates high current density vertical tunneling transistors using graphene/highly-doped silicon heterostructures, where tunneling dominates carrier transport and can be modulated by an external gate, achieving significantly higher current densities.

Contribution

It introduces a novel graphene/highly-doped silicon heterostructure for vertical tunneling transistors with enhanced current density and tunability, differing from prior graphene/insulator-based devices.

Findings

Carrier transport is dominated by tunneling through native oxide.

Tunneling current can be effectively modulated by gate voltage.

Achieved current density exceeds 20 A/cm2, two orders of magnitude higher than previous devices.

Abstract

Graphene/silicon heterostructures have attracted tremendous interest as a new platform for diverse electronic and photonic devices such as barristors, solar cells, optical modulators, and chemical sensors. The studies to date largely focus on junctions between graphene and lightly-doped silicon, where a Schottky barrier is believed to dominate the carrier transport process. Here we report a systematic investigation of carrier transport across the heterojunctions formed between graphene and highly-doped silicon. By varying the silicon doping level and the measurement temperature, we show that the carrier transport across the graphene/p++-Si heterojunction is dominated by tunneling effect through the native oxide. We further demonstrate that the tunneling current can be effectively modulated by the external gate electrical field, resulting in a vertical tunneling transistor. Benefited from the large density of states of highly doped silicon, our tunneling transistors can deliver a current density over 20 A/cm2, about two orders of magnitude higher than previous graphene/insulator/graphene tunneling transistor at the same on/off ratio.