Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures

TL;DR

This paper reviews recent advances in neuromorphic architectures using emerging non-volatile memories, focusing on design challenges like variability, energy efficiency, and wiring issues affecting large-scale systems.

Contribution

It provides a comprehensive overview of design considerations and challenges for implementing brain-inspired computing with emerging memory technologies.

Findings

Wires significantly impact large neuromorphic system performance.

Device variability and cycle-to-cycle variations affect learning accuracy.

Design targets include multilevel states and energy efficiency.

Abstract

This paper gives an overview of recent progress in the brain inspired computing field with a focus on implementation using emerging memories as electronic synapses. Design considerations and challenges such as requirements and design targets on multilevel states, device variability, programming energy, array-level connectivity, fan-in/fanout, wire energy, and IR drop are presented. Wires are increasingly important in design decisions, especially for large systems, and cycle-to-cycle variations have large impact on learning performance.