Energy-efficient optical crossbars on chip with multi-layer deposited silicon

TL;DR

This paper proposes multi-layer deposited silicon optical crossbars on chip, demonstrating significant reductions in optical losses and power consumption, thereby enhancing scalability and efficiency for multi-core systems.

Contribution

It introduces a novel multi-layer silicon deposition technique for optical crossbars, improving power efficiency and reducing losses compared to existing designs.

Findings

Ring-based network shows 22% reduction in worst-case losses.

Average loss reduction of 51.4% compared to related crossbars.

Enhanced scalability and power efficiency for multi-core chips.

Abstract

The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.