Improving Latency in a Signal Processing System on the Epiphany Architecture

TL;DR

This paper demonstrates how to optimize throughput and latency in a baseband signal processing chain on the Epiphany manycore chip using task and data parallelization along with data pipelining, leveraging its shared memory architecture.

Contribution

It introduces a method to improve latency and throughput in signal processing systems by exploiting the Epiphany chip's shared memory and parallelization capabilities.

Findings

Reduced latency in signal processing chain

Enhanced throughput through parallelization

Effective use of shared memory architecture

Abstract

In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task- and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.