Spin-Orbit Logic with Magnetoelectric Nodes: A Scalable Charge Mediated Nonvolatile Spintronic Logic

TL;DR

This paper introduces a scalable, nonvolatile spintronic logic device called MESO that leverages spin-orbit effects and magneto-electric switching, promising significant improvements in energy efficiency and device scaling for future nanoelectronics.

Contribution

It proposes the MESO logic device utilizing spin-orbit transduction and magneto-electric switching, enabling near thermodynamic limit scaling and compatibility with existing CMOS technology.

Findings

Switching energy scales cubically with device size (W^3).

Operating voltages are predicted to be below 100 mV.

MESO logic is compatible with highly resistive interconnects.

Abstract

As nanoelectronics approaches the nanometer scale, a massive effort is underway to identify the next scalable logic technology beyond Complementary Metal Oxide Semiconductor (CMOS) computing. Such computing technology needs to improve switching energy & delay at reduced dimensions, allow improved interconnects and provide a complete logic/memory family. However, a viable beyond-CMOS logic technology has remained elusive. Here, we propose a scalable spintronic logic device which operates via spin-orbit transduction combined with magneto-electric switching. The proposed Magneto-Electric Spin Orbit (MESO) logic enables a new paradigm to continue scaling of logic performance to near thermodynamic limits for GHz logic (100 kT switching energy at 100 ps delay). The proposed MESO devices scale strongly and favorably with critical dimensions of the device, showing a cubic dependence of switching energy on size, (E_m proportional to W^3), and square dependence on voltage (E_m proportional to V^2). The excellent scaling is obtained thanks to the properties of the spin orbit effects (e.g. Inverse Spin Hall Effect (ISHE) and Inverse Rashba-Edelstein Effect (IREE)) and the dependence of capacitance on size. The operating voltages for these devices are predicted to be < 100 mV allowing a significant jump ahead of historic trends of scaling voltage with size and corresponding reduction of energy. Interconnect resistance is a critical obstacle for scaling beyond 10 nm dimensions. We project a less detrimental impact of interconnect resistance and show that MESO logic is amenable for highly resistive interconnects (100 uOhm.cm-1 mOhm.cm) which opens a possibility to use nano-metallic (width < bulk electron mean free path) or doped semiconducting wires (width<5 nm). A scalable, CMOS compatible, non-volatile logic family proposed here may enable the next multi-generational scaling of computing devices.