Conductance of a SET with a retarded dielectric layer in the gate capacitor
O. G. Udalov, N. M. Chtchelkatchev, S. A. Fedorov, I. S. Beloborodov

TL;DR
This paper investigates how a ferroelectric layer with retarded response affects the conductance of a single electron transistor, revealing suppression effects, temperature-dependent behaviors, and hysteresis phenomena through Monte-Carlo simulations.
Contribution
It introduces a model for SET with a retarded ferroelectric layer, analyzing the impact on conductance and hysteresis, including the transition from fast to slow FE responses.
Findings
Retarded FE response suppresses SET conductance.
Conductance peak varies non-monotonically near Curie temperature.
Hysteresis in conductance persists below FE transition temperature.
Abstract
We study conductance of a single electron transistor (SET) with a ferroelectric (or dielectric) layer placed in the gate capacitor. We assume that ferroelectric (FE) has a retarded response with arbitrary relaxation time. We show that in the case of "fast" but still retarded response of the FE (dielectric) layer an additional contribution to the Coulomb blockade effect appears leading to the suppression of the SET conductance. We take into account fluctuations of the FE (dielectric) polarization using Monte-Carlo simulations. For "fast" FE these fluctuations partially suppress the additional Coulomb blockade effect. Using Monte-Carlo simulations we study the transition from "fast" to "slow" FE. For high temperatures the peak value of the SET conductance is almost independent of the FE relaxation time. For temperatures close to the FE Curie temperature the conductance peak value…
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