Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

TL;DR

This paper presents a digital LDO design using time-interleaved comparators to improve response speed and reduce ripple, achieving high efficiency and fast settling times suitable for multi-core processors.

Contribution

The work introduces a novel digital LDO topology with time-interleaved comparators to overcome comparator offset issues at high frequencies.

Findings

Achieves less than 5mV ripple for 50mA load step

Settling time under 0.5 microseconds

Maintains ~97% current efficiency with dynamic clock adjustment

Abstract

On-chip voltage regulation using distributed Digital Low Drop Out (LDO) voltage regulators has been identified as a promising technique for efficient power-management for emerging multi-core processors. Digital LDOs (DLDO) can offer low voltage operation, faster transient response, and higher current efficiency. Response time as well as output voltage ripple can be reduced by increasing the speed of the dynamic comparators. However, the comparator offset steeply increases for high clock frequencies, thereby leading to enhanced variations in output voltage. In this work we explore the design of digital LDOs with multiple dynamic comparators that can overcome this bottleneck. In the proposed topology, we apply time-interleaved comparators with the same voltage threshold and uniform current step in order to accomplish the aforementioned features. Simulation based analysis shows that the DLDO with time-interleaved comparators can achieve better overall performance in terms of current efficiency, ripple and settling time. For a load step of 50mA, a DLDO with 8 time-interleaved comparators could achieve an output ripple of less than 5mV, while achieving a settling time of less than 0.5us. Load current dependant dynamic adjustment of clock frequency is proposed to maintain high current efficiency of ~97%.