Generating Configurable Hardware from Parallel Patterns

TL;DR

This paper introduces a high-level approach for generating efficient FPGA hardware from parallel patterns, using tiling and metapipelining optimizations, achieving significant speedups in data analytics benchmarks.

Contribution

It presents a novel method for automatic tiling and metapipelining of parallel patterns to improve FPGA hardware generation from high-level functional languages.

Findings

Achieved up to 40x speedup on data analytics benchmarks.

Developed a general representation for tiled parallel patterns.

Provided rules for automatic tiling and metapipeline generation.

Abstract

In recent years the computing landscape has seen an in- creasing shift towards specialized accelerators. Field pro- grammable gate arrays (FPGAs) are particularly promising as they offer significant performance and energy improvements compared to CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the pro- ductivity features of modern software development languages but produce very efficient designs, and low-level software lan- guages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they both provide high-level abstractions to programmers with little experience in hard- ware design and avoid many of the problems faced when gen- erating hardware from imperative languages. In this paper, we identify two optimizations that are important when using par- allel patterns to generate hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and gen- erating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 40x on a set of benchmarks from the data analytics domain.