Testable Design of Repeaterless Low Swing On-Chip Interconnect

TL;DR

This paper presents a testable design for repeaterless low swing on-chip interconnects, combining mixed signal techniques and scan testing to achieve high fault coverage with low overhead in CMOS technology.

Contribution

It introduces a test methodology integrating analog and digital components for high fault coverage in low swing interconnects.

Findings

DC test covers 50% of faults

Scan chain integration increases coverage to 74%

BIST achieves 95% fault coverage

Abstract

Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology.