Experimental Demonstration of Single Electron Transistors Featuring SiO2 PEALD in Ni-SiO2-Ni Tunnel Junctions

TL;DR

This paper demonstrates the fabrication of single-electron transistors with ultra-thin SiO2 tunnel barriers using PEALD, highlighting the impact of parasitic NiO layers and their reduction via thermal annealing to restore proper device function.

Contribution

The study introduces a PEALD-based fabrication process for Ni-SiO2-Ni SETs and shows how thermal annealing reduces parasitic NiO layers, improving device performance.

Findings

PEALD causes oxidation of Ni surfaces, forming NiO layers.

Parasitic NiO layers increase resistance and alter transport mechanisms.

Thermal annealing reduces NiO, restoring tunnel junction properties.

Abstract

We report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultra-thin (~1 nm) tunnel-transparent SiO2 in Ni-SiO2-Ni tunnel junctions. We show that as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni-SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) structure of the junctions. Rapid thermal annealing in a forming gas ambient at elevated temperatures is presented as a technique to reduce both parasitic oxide layers. This method is of great interest for devices that rely on MIM tunnel junctions with ultra-thin barriers. Using this technique, we successfully fabricated MIM SETs with minimal trace of parasitic NiO component. We demonstrate that the properties of the tunnel barrier in nanoscale tunnel junctions can be evaluated by electrical characterization of SETs.