Network-on-Chip with load balancing based on interleave of flits technique

TL;DR

This paper evaluates a load balancing Network-on-Chip technique that interleaves flits from different flows using embedded routing info, improving latency under high traffic for multimedia SoCs.

Contribution

It introduces a flit interleaving method with embedded routing info for load balancing in NoCs without centralized control, enhancing performance under high load.

Findings

Lower average latency for variable bitrate flows at over 80% load.

Effective load balancing without centralized control.

Improved performance over resource reservation methods.

Abstract

This paper presents the evaluation of a Network-on-Chip (NoC) that offers load balancing for Systems-on-Chip (SoCs) dedicated for multimedia applications that require high traffic of variable bitrate communication. The NoC is based on a technique that allows the interleaving of flits from diferente flows in the same communication channel, and keep the load balancing without a centralized control in the network. For this purpose, all flits in the network received extra bits, such that every flit carries routing information. The routers use this extra information to perform arbitration and schedule the flits to the corresponding output ports. Analytic comparisons and experimental data show that the approach adopted in the network keeps average latency lower for variable bitrate flows than a network based on resource reservation when both networks are working over 80% of offered load.