Optimization of an electromagnetics code with multicore wavefront diamond blocking and multi-dimensional intra-tile parallelization

TL;DR

This paper presents a novel optimization technique for a computational electromagnetics code, significantly improving performance by applying multicore wavefront diamond tiling and multi-dimensional intra-tile parallelization, effectively overcoming memory bandwidth limitations.

Contribution

It introduces a specialized stencil optimization method tailored for a unique electromagnetic simulation algorithm, with detailed modeling and auto-tuning for optimal performance.

Findings

Achieved 3-4x speedup over traditional spatial blocking methods.

Decoupled execution from memory bandwidth bottleneck.

Validated the effectiveness of the optimization on an 18-core CPU.

Abstract

Understanding and optimizing the properties of solar cells is becoming a key issue in the search for alternatives to nuclear and fossil energy sources. A theoretical analysis via numerical simulations involves solving Maxwell's Equations in discretized form and typically requires substantial computing effort. We start from a hybrid-parallel (MPI+OpenMP) production code that implements the Time Harmonic Inverse Iteration Method (THIIM) with Finite-Difference Frequency Domain (FDFD) discretization. Although this algorithm has the characteristics of a strongly bandwidth-bound stencil update scheme, it is significantly different from the popular stencil types that have been exhaustively studied in the high performance computing literature to date. We apply a recently developed stencil optimization technique, multicore wavefront diamond tiling with multi-dimensional cache block sharing, and describe in detail the peculiarities that need to be considered due to the special stencil structure. Concurrency in updating the components of the electric and magnetic fields provides an additional level of parallelism. The dependence of the cache size requirement of the optimized code on the blocking parameters is modeled accurately, and an auto-tuner searches for optimal configurations in the remaining parameter space. We were able to completely decouple the execution from the memory bandwidth bottleneck, accelerating the implementation by a factor of three to four compared to an optimal implementation with pure spatial blocking on an 18-core Intel Haswell CPU.