Memory-Efficient Design Strategy for a Parallel Embedded Integral Image Computation Engine

TL;DR

This paper introduces a memory-efficient parallel integral image computation engine for embedded vision systems, significantly reducing memory usage while maintaining high throughput for HD video processing.

Contribution

It proposes a novel design strategy that minimizes internal memory requirements without sacrificing processing speed in embedded integral image computation.

Findings

Achieves nearly 35% reduction in memory for HD video

Maintains high throughput in embedded systems

Reduces hardware resource usage significantly

Abstract

In embedded vision systems, parallel computation of the integral image presents several design challenges in terms of hardware resources, speed and power consumption. Although recursive equations significantly reduce the number of operations for computing the integral image, the required internal memory becomes prohibitively large for an embedded integral image computation engine for increasing image sizes. With the objective of achieving high-throughput with minimum hardware resources, this paper proposes a memory-efficient design strategy for a parallel embedded integral image computation engine. Results show that the design achieves nearly 35% reduction in memory for common HD video.