Reproducible Operating Margins on a 72,800-Device Digital Superconducting Chip

TL;DR

This paper reports the design and testing of the largest digital superconducting circuits to date, demonstrating large operating margins and reproducibility across thermal cycles, indicating flux-trapping is no longer a limiting factor.

Contribution

It presents the design, fabrication, and testing of superconducting shift-register circuits with up to 72,800 Josephson junctions, showing large operating margins and reproducibility, advancing large-scale superconducting digital logic.

Findings

Largest superconducting digital circuits reported to date.

Achieved ±20% operating margins on AC clock amplitude.

Reproducibility of measurements across thermal cycles with minimal shielding.

Abstract

We report the design and test of Reciprocal Quantum Logic shift-register yield vehicles consisting of up to 72,800 Josephson junction devices per die, the largest digital superconducting circuits ever reported. Multiple physical layout styles were matched to the MIT Lincoln Laboratory foundry, which supports processes with both four and eight metal layers and minimum feature size of 0.5 {\mu}m. The largest individual circuits with 40,400 junctions indicate large operating margins of $\pm$20% on AC clock amplitude. In one case the data were reproducible to the accuracy of the measurement, $\pm$1% across five thermal cycles using only the rudimentary precautions of passive mu-metal magnetic shielding and a controlled cool-down rate of 3 mK/s in the test fixture. We conclude that with proper mitigation techniques, flux-trapping is no longer a limiting consideration for very-large-scale-integration of superconductor digital logic.