Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems

TL;DR

This paper presents a hybrid spintronic-CMOS spiking neural network with on-chip learning, featuring a novel spintronic synapse that enables low-energy, fast programming for pattern recognition applications.

Contribution

It introduces a decoupled spike transmission and programming current spintronic synapse integrated with CMOS neurons for on-chip learning.

Findings

Low programming energy demonstrated for the spintronic synapse

Fast programming times achieved in device simulations

Successful interfacing of spintronic synapses with CMOS neurons for pattern recognition

Abstract

Over the past decade Spiking Neural Networks (SNN) have emerged as one of the popular architectures to emulate the brain. In SNN, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing dependent plasticity mechanisms require the online programming of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike transmission and programming current paths. The spintronic synapse consists of a ferromagnet-heavy metal heterostructure where programming current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programming energy and fast programming times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in transistor sub-threshold region to form a network of spiking neurons that can be utilized for pattern recognition problems.