VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

TL;DR

This paper presents an integral stochastic computing approach for deep neural networks, achieving significant reductions in area, latency, and energy consumption on FPGA and CMOS implementations, enhancing efficiency and fault tolerance.

Contribution

It introduces an integer form of stochastic computation and an efficient DNN architecture, improving upon existing stochastic methods in hardware efficiency and energy savings.

Findings

45% reduction in area on FPGA

62% reduction in latency on FPGA

21% reduction in energy consumption in CMOS

Abstract

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral stochastic computing. The proposed architecture has been implemented on a Virtex7 FPGA, resulting in 45% and 62% average reductions in area and latency compared to the best reported architecture in literature. We also synthesize the circuits in a 65 nm CMOS technology and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared to the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation which yields 33% reduction in energy consumption w.r.t. the binary radix implementation without any compromise on performance.