Automatic latency balancing in VHDL-implemented complex pipelined systems

TL;DR

This paper introduces an automatic, simulation-based method for balancing latency in VHDL-implemented pipelined systems, reducing manual effort and errors while maintaining design complexity.

Contribution

It presents a portable, non-intrusive approach for automatic latency equalization in VHDL systems, compatible with various tools and open source.

Findings

Method is portable across simulation and synthesis tools.

It does not increase design complexity.

Open source implementation is available.

Abstract

Balancing (equalization) of latency in parallel paths in the pipelined data processing system is an important problem. Without that the data from different paths arrive at the processing blocks in different clock cycles, and incorrect results are produced. Manual correction of latencies is a tedious and error-prone work. This paper presents an automatic method of latency equalization in systems described in VHDL. The method is based on simulation and is portable between different simulation and synthesis tools. The method does not increase the complexity of the synthesized design comparing to the solution based on manual latency adjustment. The example implementation of the proposed methodology together with a simple design demonstrating its use is available as an open source project under BSD license.