A 128 channel Extreme Learning Machine based Neural Decoder for Brain Machine Interfaces

TL;DR

This paper introduces a low-power, 128-channel neural decoder chip based on Extreme Learning Machine for brain-machine interfaces, achieving high accuracy and energy efficiency in decoding motor intentions from neural data.

Contribution

It presents a novel 0.35um CMOS co-processor implementing ELM for neural decoding, with enhanced robustness, accuracy, and reduced weight complexity compared to prior systems.

Findings

Achieves 99.3% decoding accuracy for movement type

Energy efficiency of 290 GMACs/W at 50 Hz

Reduces programmable weights by approximately 2 times

Abstract

Currently, state-of-the-art motor intention decoding algorithms in brain-machine interfaces are mostly implemented on a PC and consume significant amount of power. A machine learning co-processor in 0.35um CMOS for motor intention decoding in brain-machine interfaces is presented in this paper. Using Extreme Learning Machine algorithm and low-power analog processing, it achieves an energy efficiency of 290 GMACs/W at a classification rate of 50 Hz. The learning in second stage and corresponding digitally stored coefficients are used to increase robustness of the core analog processor. The chip is verified with neural data recorded in monkey finger movements experiment, achieving a decoding accuracy of 99.3% for movement type. The same co-processor is also used to decode time of movement from asynchronous neural spikes. With time-delayed feature dimension enhancement, the classification accuracy can be increased by 5% with limited number of input channels. Further, a sparsity promoting training scheme enables reduction of number of programmable weights by ~2X.