FPGA Implementation of a Fixed Latency Scheme in a Signal Packet Router for the Upgrade of ATLAS Forward Muon Trigger Electronics

TL;DR

This paper presents a novel fixed latency scheme implemented in FPGA for high-speed data links, enhancing the ATLAS muon trigger upgrade with protocol-independent, resource-efficient design.

Contribution

The paper introduces a new fixed latency scheme using FPGA resources that is protocol independent and adaptable to different FPGA vendors.

Findings

Successful implementation in Xilinx FPGA at 4.8 Gbps

Simulation results confirm fixed latency performance in real environment

Scheme minimizes reliance on embedded transceiver features

Abstract

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a frontend data serializer ASIC and a packet router. To achieve fixed latency, we use IO delay and dedicated carry in resources in a Xilinx FPGA, while minimally relying on the embedded features of the FPGA transceivers. The scheme is protocol independent and can be adapted to FPGA from other vendors with similar resources. This paper presents a detailed implementation of the fixed latency scheme, as well as simulations of the real environment in the ATLAS forward muon region.