Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector

TL;DR

This paper presents the design and testing of a serializer ASIC for the ATLAS muon detector upgrade, demonstrating high data rate performance, low error rate, and low power consumption.

Contribution

It introduces a new serializer ASIC prototype optimized for high-speed data transmission in particle physics detectors.

Findings

Serializer operates at least at 5.76 Gbps with low error rate

Power consumption is 200 mW at 4.8 Gbps

Latency is approximately 6 ns

Abstract

We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns.