A balanced rail-to-rail all digital comparator using only standard cells

TL;DR

This paper introduces a fully digital, rail-to-rail comparator utilizing a novel Yin-yang balancing mechanism between NAND3 and OAI gates, achieving wide input range and efficient implementation in standard CMOS technology.

Contribution

It proposes a new Yin-yang balance mechanism for all-digital comparators, enabling full input range and automatic layout generation using standard cells.

Findings

Achieves large rail-to-rail input range

Power consumption of 0.176mW at 330MHz

Implemented in 130nm CMOS technology

Abstract

An all-digital comparator with full input range is presented. It outperforms the nowaday all-digital comparators with its large rail-to-rail input range. This is achieved by the proposed Yin-yang balance mechanism between the two logic gates: NAND3 and OAI (Or-And-Invert). The important design considerations to achieve this balance are presented, such as the driving strength manipulation and the use of pre-distortion technique. Constructed only by commercially available digital standard cells, the layout of the proposed comparator is generated automatically by standard digital Place & Route routine within several minutes. The Verilog code for the proposed circuit is given, and the circuit is successfully implemented in 130nm CMOS technology with the power consumption of 0.176mW at the clock of 330MHz.