Evolution of structure of some binary group based n bit comparator, n-to-2n decoder by reversible technique

TL;DR

This paper introduces a new reversible logic gate and designs various reversible comparators and decoders, demonstrating improvements in power, delay, and efficiency for low power VLSI applications.

Contribution

A novel 4x4 reversible gate called inventive gate is proposed, enabling efficient construction of multi-bit comparators and n-to-2n decoders with improved parameters.

Findings

Proposed reversible comparator designs have lower power consumption.

The inventive gate reduces the number of gates and garbage outputs.

MOS implementations show favorable power, delay, and PDP metrics.

Abstract

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2- bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n decoder. Different proposed novel reversible circuit design style is compared with the existing ones. The relative results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms the present design style in terms of number of gates, garbage outputs and constant input.