Hardware Implementation of Compressed Sensing based Low Complex Video Encoder

TL;DR

This paper introduces a low-complexity, memory-efficient VLSI architecture for video encoding using 3-D wavelet transforms and compressed sensing, reducing complexity and power consumption for space-constrained applications.

Contribution

It presents the first VLSI architecture combining 3-D DWT and compressed sensing for low-power, scalable video encoding with reduced memory and high throughput.

Findings

Consumes 90.08 mW power at 158 MHz

Requires significantly less memory than existing architectures

Achieves high throughput with low complexity

Abstract

This paper presents a memory efficient VLSI architecture of low complex video encoder using three dimensional (3-D) wavelet and Compressed Sensing (CS) is proposed for space and low power video applications. Majority of the conventional video coding schemes are based on hybrid model, which requires complex operations like transform coding (DCT), motion estimation and deblocking filter at the encoder. Complexity of the proposed encoder is reduced by replacing those complex operations by 3-D DWT and CS at the encoder. The proposed architecture uses 3-D DWT to enable the scalability with levels of wavelet decomposition and also to exploit the spatial and the temporal redundancies. CS provides the good error resilience and coding efficiency. At the first stage of the proposed architecture for encoder, 3-D DWT has been applied (Lifting based 2-D DWT in spatial domain and Haar wavelet in temporal domain) on each frame of the group of frames (GOF), and in the second stage CS module exploits the sparsity of the wavelet coefficients. Small set of linear measurements are extracted by projecting the sparse 3-D wavelet coefficients onto random Bernoulli matrix at the encoder. Compared with the best existing 3-D DWT architectures, the proposed architecture for 3-D DWT requires less memory and provide high throughput. For an N?N image, the proposed 3-D DWT architecture consumes a total of only 2?(3N +40P) words of on-chip memory for the one level of decomposition. The proposed architecture for an encoder is first of its kind and to the best of my knowledge, no architecture is noted for comparison. The proposed VLSI architecture of the encoder has been synthesized on 90-nm CMOS process technology and results show that it consumes 90.08 mW power and occupies an area equivalent to 416.799 K equivalent gate at frequency of 158 MHz.