FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic

TL;DR

This paper presents an FPGA implementation of a high-speed Baugh-Wooley multiplier enhanced with decomposition logic, achieving faster performance and reduced delay compared to traditional methods, demonstrated on Xilinx FPGA.

Contribution

The paper introduces a novel FPGA-based high-speed multiplier combining Baugh-Wooley algorithm with decomposition logic for improved performance.

Findings

Achieved faster multiplication speed using decomposition logic

Reduced critical path delay compared to conventional multipliers

Implemented and tested on Xilinx FPGA platform

Abstract

The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.