Three-Dimensional Stateful Material Implication Logic

TL;DR

This paper demonstrates reliable multi-cycle, multi-gate memristor-based logic operations in a 3D monolithic stack, enabling compact, high-throughput in-memory computing and addressing key challenges in nanoscale logic-in-memory systems.

Contribution

It introduces a low-variability fabrication process and circuit modifications that enable robust, multi-cycle memristor logic in three dimensions, advancing in-memory computing technology.

Findings

Successful multi-cycle, multi-gate logic operations in 3D memristor stacks.

Enhanced robustness to device variability through circuit design.

Potential for nanoscale 8-bit adder implementation.

Abstract

Monolithic three-dimensional integration of memory and logic circuits could dramatically improve performance and energy efficiency of computing systems. Some conventional and emerging memories are suitable for vertical integration, including highly scalable metal-oxide resistive switching devices (memristors), yet integration of logic circuits proves to be much more challenging. Here we demonstrate memory and logic functionality in a monolithic three-dimensional circuit by adapting recently proposed memristor-based stateful material implication logic. Though such logic has been already implemented with a variety of memory devices, prohibitively large device variability in the most prospective memristor-based circuits has limited experimental demonstrations to simple gates and just a few cycles of operations. By developing a low-temperature, low-variability fabrication process, and modifying the original circuit to increase its robustness to device imperfections, we experimentally show, for the first time, reliable multi-cycle multi-gate material implication logic operation within a three-dimensional stack of monolithically integrated memristors. The direct data manipulation in three dimensions enables extremely compact and high-throughput logic-in-memory computing and, remarkably, presents a viable solution for the Feynman grand challenge of implementing an 8-bit adder at the nanoscale.