Characterizing a Four-Qubit Planar Lattice for Arbitrary Error Detection

TL;DR

This paper details the characterization and calibration of a four-qubit superconducting lattice designed for surface code error detection, demonstrating key gate operations and system insights relevant for scalable quantum computing.

Contribution

It provides experimental procedures, calibration results, and system insights for a four-qubit superconducting lattice suitable for surface code implementation.

Findings

Successful calibration of single- and two-qubit gates

Benchmarking results for two-qubit gate pairs

Insights into qubit design and parameter comparison

Abstract

Quantum error correction will be a necessary component towards realizing scalable quantum computers with physical qubits. Theoretically, it is possible to perform arbitrarily long computations if the error rate is below a threshold value. The two-dimensional surface code permits relatively high fault-tolerant thresholds at the ~1% level, and only requires a latticed network of qubits with nearest-neighbor interactions. Superconducting qubits have continued to steadily improve in coherence, gate, and readout fidelities, to become a leading candidate for implementation into larger quantum networks. Here we describe characterization experiments and calibration of a system of four superconducting qubits arranged in a planar lattice, amenable to the surface code. Insights into the particular qubit design and comparison between simulated parameters and experimentally determined parameters are given. Single- and two-qubit gate tune-up procedures are described and results for simultaneously benchmarking pairs of two-qubit gates are given. All controls are eventually used for an arbitrary error detection protocol described in separate work [Corcoles et al., Nature Communications, 6, 2015]