Applying Multi-Core Model Checking to Hardware-Software Partitioning in Embedded Systems (extended version)

TL;DR

This paper introduces a multi-core SMT-based Bounded Model Checking approach for hardware-software partitioning in embedded systems, demonstrating its effectiveness in finding optimal solutions compared to traditional methods.

Contribution

It presents a novel multi-core SMT-based BMC method for HW-SW partitioning, leveraging parallel verification instances to improve optimization efficiency.

Findings

Outperforms Integer Linear Programming in certain cases

Comparable or better results than Genetic Algorithm

Effective in finding optimal HW-SW partitioning solutions

Abstract

We present an alternative approach to solve the hardware (HW) and software (SW) partitioning problem, which uses Bounded Model Checking (BMC) based on Satisfiability Modulo Theories (SMT) in conjunction with a multi-core support using Open Multi-Processing. The multi-core SMT-based BMC approach allows initializing many verification instances based on processors cores numbers available to the model checker. Each instance checks for a different optimum value until the optimization problem is satisfied. The goal is to show that multi-core model-checking techniques can be effective, in particular cases, to find the optimal solution of the HW-SW partitioning problem using an SMT-based BMC approach. We compare the experimental results of our proposed approach with Integer Linear Programming and the Genetic Algorithm.