Dissecting GPU Memory Hierarchy through Microbenchmarking

TL;DR

This paper introduces a microbenchmarking method to analyze GPU memory hierarchies across three NVIDIA GPU generations, revealing new insights into cache structures, memory throughput, and latency to aid optimization.

Contribution

It presents the first detailed characterization of cache properties in Kepler and Maxwell GPUs, enhancing understanding of GPU memory behavior for software optimization.

Findings

Revealed cache structures of Kepler and Maxwell GPUs

Compared throughput and latency of global and shared memory

Identified Maxwell's superior shared memory performance under bank conflicts

Abstract

Memory access efficiency is a key factor in fully utilizing the computational power of graphics processing units (GPUs). However, many details of the GPU memory hierarchy are not released by GPU vendors. In this paper, we propose a novel fine-grained microbenchmarking approach and apply it to three generations of NVIDIA GPUs, namely Fermi, Kepler and Maxwell, to expose the previously unknown characteristics of their memory hierarchies. Specifically, we investigate the structures of different GPU cache systems, such as the data cache, the texture cache and the translation look-aside buffer (TLB). We also investigate the throughput and access latency of GPU global memory and shared memory. Our microbenchmark results offer a better understanding of the mysterious GPU memory hierarchy, which will facilitate the software optimization and modelling of GPU architectures. To the best of our knowledge, this is the first study to reveal the cache properties of Kepler and Maxwell GPUs, and the superiority of Maxwell in shared memory performance under bank conflict.