A macro placer algorithm for chip design

TL;DR

This paper introduces a heuristic macro placement algorithm for chip design that uses a specialized data structure for efficient computation of two-dimensional stepfunctions, improving placement efficiency.

Contribution

The paper presents a novel heuristic algorithm utilizing a unique data structure for 2D stepfunctions to optimize macro placement in chip design.

Findings

Efficient placement of macros with minimized wire length.

Fast computation of 2D stepfunctions for placement.

Potential applicability of the data structure in other areas.

Abstract

There is a set of rectangular macros with given dimensions, and there are wires connecting some pairs (or sets) of them. We have a placement area where these macros should be placed without overlaps in order to minimize the total length of wires. We present a heuristic algorithm which utilizes a special data structure for representing two dimensional stepfunctions. This results in fast integral computation and function modification over rectangles. Our heuristics, especially our data structure for two-dimensional functions, may be useful in other applications, as well.