Improving Charge-Collection Efficiency of Kyoto's SOI Pixel Sensors

TL;DR

This paper improves the charge-collection efficiency of Kyoto's SOI pixel sensors for X-ray astronomy by analyzing electric field effects and optimizing pixel circuitry placement, leading to enhanced performance at pixel borders.

Contribution

The study identifies electric field-induced charge trapping as a cause of CCE degradation and proposes a circuitry placement modification to mitigate this issue.

Findings

CCE at pixel borders is improved with circuitry placement changes

Electric field simulation explains charge trapping at pixel edges

Modified design maintains imaging spectroscopy performance

Abstract

We have been developing X-ray SOIPIXs for next-generation satellites for X-ray astronomy. Their high time resolution ($\sim10~\mu$s) and event-trigger-output function enable us to read out without pile-ups and to use anti-coincidence systems. Their performance in imaging spectroscopy is comparable to that in the CCDs. A problem in our previous model was degradation of charge-collection efficiency (CCE) at pixel borders. We measured the response in the sub-pixel scale, using finely collimated X-ray beams at $10~\mu$m\Phi$ at SPring-8, and investigated the non-uniformity of the CCE within a pixel. We found that the X-ray detection efficiency and CCE degrade in the sensor region under the pixel circuitry placed outside the buried p-wells (BPW). A 2D simulation of the electric fields shows that the isolated pixel-circuitry outside the BPW creates local minimums in the electric potentials at the interface between the sensor and buried oxide layers. Thus, a part of signal charge is trapped there and is not collected to the BPW. Based on this result, we modified the placement of the in-pixel circuitry so that the electric fields would converge toward the BPW. We confirmed that the CCE at pixel borders is successfully improved with the updated model.