Recognizing and Drawing IC-planar Graphs

TL;DR

This paper presents efficient algorithms for drawing IC-planar graphs with optimal area and proves the NP-completeness of IC-planarity testing, along with a polynomial-time method for augmenting planar graphs to IC-planar graphs.

Contribution

It introduces optimal-area algorithms for straight-line IC-planar graph drawings and establishes NP-completeness of IC-planarity testing, also providing a polynomial-time augmentation method.

Findings

Linear-time algorithm for straight-line drawing in quadratic area

Exponential-area drawing with right-angle crossings

NP-completeness of IC-planarity testing

Abstract

IC-planar graphs are those graphs that admit a drawing where no two crossed edges share an end-vertex and each edge is crossed at most once. They are a proper subfamily of the 1-planar graphs. Given an embedded IC-planar graph $G$ with $n$ vertices, we present an $O(n)$-time algorithm that computes a straight-line drawing of $G$ in quadratic area, and an $O(n^3)$-time algorithm that computes a straight-line drawing of $G$ with right-angle crossings in exponential area. Both these area requirements are worst-case optimal. We also show that it is NP-complete to test IC-planarity both in the general case and in the case in which a rotation system is fixed for the input graph. Furthermore, we describe a polynomial-time algorithm to test whether a set of matching edges can be added to a triangulated planar graph such that the resulting graph is IC-planar.