OpenCL 2.0 for FPGAs using OCLAcc

TL;DR

This paper introduces OCLAcc, a tool that facilitates FPGA hardware accelerator design from OpenCL 2.0, enabling higher-level abstraction, faster development, and iterative testing for embedded and high-performance applications.

Contribution

OCLAcc is a novel tool that translates OpenCL 2.0 specifications into FPGA hardware accelerators, simplifying and accelerating the hardware design process.

Findings

Enables FPGA accelerator generation from OpenCL 2.0

Reduces development time for FPGA hardware

Supports iterative testing and optimization

Abstract

Designing hardware is a time-consuming and complex process. Realization of both, embedded and high-performance applications can benefit from a design process on a higher level of abstraction. This helps to reduce development time and allows to iteratively test and optimize the hardware design during development, as common in software development. We present our tool, OCLAcc, which allows the generation of entire FPGA-based hardware accelerators from OpenCL and discuss the major novelties of OpenCL 2.0 and how they can be realized in hardware using OCLAcc.