Suppression of Surface-Originated Gate-Lag by a Dual-Channel AlN/GaN HEMT Architecture

TL;DR

This paper introduces a dual-channel AlN/GaN HEMT architecture that uses ultra-thin layers to significantly reduce surface-related gate lag, improving device stability and performance.

Contribution

It demonstrates a novel dual-channel heterostructure design with ultra-thin layers that suppresses gate lag and enhances high-frequency performance.

Findings

Recessed-gate HEMT achieved a gate lag ratio of 0.88 with no drain current collapse.

Non-recessed HEMT showed a gate lag ratio of 0.74 and 82 mA/mm current collapse.

Recessed-gate device maintained high small signal metrics of 27/46 GHz.

Abstract

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-state related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from surface and interface trapped charge. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing HVPE GaN substrates where 300 nm long recessed and non-recessed gate HEMTs were fabricated. The recessed-gate HEMT demonstrated a gate lag ratio (GLR) of 0.88 with no collapse in drain current and supporting small signal metrics $f_t/f_{max}$ of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with $f_t/f_{max}$ of 48/60 GHz.