RIPL: An Efficient Image Processing DSL for FPGAs

TL;DR

RIPL is a domain-specific language designed for FPGAs that enables efficient, highly concurrent image processing pipelines by leveraging algorithmic skeletons and tailored hardware models.

Contribution

It introduces RIPL, a new FPGA-oriented image processing DSL with algorithmic skeletons for optimized pipeline generation.

Findings

Enables deep, memory-efficient pipelines

Achieves high concurrency in FPGA implementations

Improves hardware utilization for image processing

Abstract

Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting fine-grained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL, an image processing domain specific language (DSL) for FPGAs. It has algorithmic skeletons to express image processing, and these are exploited to generate deep pipelines of highly concurrent and memory-efficient image processing components.