A Holistic Approach in Embedded System Development

TL;DR

This paper introduces pState, a tool that integrates validation into embedded system design using intuitive property specification in pCharts, enabling automatic code generation that preserves verified properties, thereby streamlining validation and documentation.

Contribution

The paper presents pState, a novel tool that simplifies property specification and automates code generation for embedded systems, reducing validation time and effort.

Findings

Effective property specification without temporal logic expertise

Automated code generation preserves system properties

Reduced validation and documentation effort

Abstract

We present pState, a tool for developing "complex" embedded systems by integrating validation into the design process. The goal is to reduce validation time. To this end, qualitative and quantitative properties are specified in system models expressed as pCharts, an extended version of hierarchical state machines. These properties are specified in an intuitive way such that they can be written by engineers who are domain experts, without needing to be familiar with temporal logic. From the system model, executable code that preserves the verified properties is generated. The design is documented on the model and the documentation is passed as comments into the generated code. On the series of examples we illustrate how models and properties are specified using pState.