Quantum Photonic Interconnect

TL;DR

This paper demonstrates a high-fidelity quantum photonic interconnect between two separate silicon chips, enabling entanglement distribution and manipulation crucial for scalable quantum computing and communication systems.

Contribution

It introduces a novel integrated photonic interconnect that coherently distributes entanglement between chips using state-of-the-art silicon photonics.

Findings

Achieved Bell inequality violation with S=2.638+-0.039 between chips

Generated and manipulated path-entangled states on-chip

Distributed entanglement via path- and polarization-encoding interconversion

Abstract

Integrated photonics has enabled much progress towards quantum technologies. Many applications, including quantum communication, sensing, and distributed and cloud quantum computing, will require coherent photonic interconnection between separate chip-based sub-systems. Large-scale quantum computing systems and architectures may ultimately require quantum interconnects to enable scaling beyond the limits of a single wafer and towards "multi-chip" systems. However, coherently interconnecting separate chips is challenging due to the fragility of these quantum states and the demanding challenges of transmitting photons in at least two media within a single coherent system. Distribution and manipulation of qubit entanglement between multiple devices is one of the most stringent requirements of the interconnected system. Here, we report a quantum photonic interconnect demonstrating high-fidelity entanglement distribution and manipulation between two separate chips, implemented using state-of-the-art silicon photonics. Path-entangled states are generated and manipulated on-chip, and distributed between the chips by interconverting between path-encoding and polarisation-encoding. We use integrated state analysers to confirm a Bell-type violation of $S$=2.638+-0.039 between two chips. With improvements in loss, this quantum interconnect will provide new levels of flexible systems and architectures for quantum technologies.