The effect of split gate size on the electrostatic potential and 0.7 anomaly within one-dimensional quantum wires on a modulation doped GaAs/AlGaAs heterostructure

TL;DR

This study investigates how split gate size affects electrostatic potential and the 0.7 conductance anomaly in one-dimensional quantum wires on GaAs/AlGaAs heterostructures, revealing the importance of electrostatic environment and background potential fluctuations.

Contribution

It provides a comprehensive analysis of the relationship between gate size, electrostatic potential, and conductance anomalies, highlighting the role of background potential fluctuations in device behavior.

Findings

Device yield decreases with increasing gate length.

No correlation between electrostatic length and gate length for good devices.

Barrier curvature influences the 0.7 anomaly strength.

Abstract

We study 95 split gates of different size on a single chip using a multiplexing technique. Each split gate defines a one-dimensional channel on a modulation-doped GaAs/AlGaAs heterostructure, through which the conductance is quantized. The yield of devices showing good quantization decreases rapidly as the length of the split gates increases. However, for the subset of devices showing good quantization, there is no correlation between the electrostatic length of the one dimensional channel (estimated using a saddle point model), and the gate length. The variation in electrostatic length and the one-dimensional subband spacing for devices of the same gate length exceeds the variation in the average values between devices of different length. There is a clear correlation between the curvature of the potential barrier in the transport direction and the strength of the "0.7 anomaly": the conductance value of the 0.7 anomaly reduces as the barrier curvature becomes shallower. These results highlight the key role of the electrostatic environment in one-dimensional systems. Even in devices with clean conductance plateaus, random fluctuations in the background potential are crucial in determining the potential landscape in the active device area such that nominally identical gate structures have different characteristics.