Majority Logic Decoding under Data-Dependent Logic Gate Failures

TL;DR

This paper analyzes the performance of majority logic decoders built from unreliable, data-dependent logic gates, deriving error rate formulas and bounds, and demonstrating fault-tolerant error correction capabilities for LDPC codes.

Contribution

It introduces a combinatorial analysis framework for faulty decoders with data-dependent failures and proves their ability to correct a fixed fraction of errors.

Findings

Derived a closed-form expression for average bit error rate.

Established bounds on decoder performance under data-dependent failures.

Proven fault-tolerant error correction for LDPC codes with faulty decoders.

Abstract

A majority logic decoder made of unreliable logic gates, whose failures are transient and datadependent, is analyzed. Based on a combinatorial representation of fault configurations a closed-form expression for the average bit error rate for an one-step majority logic decoder is derived, for a regular low-density parity-check (LDPC) code ensemble and the proposed failure model. The presented analysis framework is then used to establish bounds on the one-step majority logic decoder performance under the simplified probabilistic gate-output switching model. Based on the expander property of Tanner graphs of LDPC codes, it is proven that a version of the faulty parallel bit flipping decoder can correct a fixed fraction of channel errors in the presence of data-dependent gate failures. The results are illustrated with numerical examples of finite geometry codes.