Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors

TL;DR

This paper investigates optimizing matrix multiplication on asymmetric big.LITTLE ARM processors, focusing on balancing performance and energy efficiency for mobile and high-performance computing environments.

Contribution

It presents the first adaptation of the BLAS interface for asymmetric ARM big.LITTLE processors, analyzing performance-energy trade-offs.

Findings

Significant performance gains achieved.

Maintains energy efficiency comparable to homogeneous solutions.

Efficient resource utilization in asymmetric processors.

Abstract

Asymmetric processors have emerged as an appealing technology for severely energy-constrained environments, especially in the mobile market where heterogeneity in applications is mainstream. In addition, given the growing interest on ultra low-power architectures for high performance computing, this type of platforms are also being investigated in the road towards the implementation of energy- efficient high-performance scientific applications. In this paper, we propose a first step towards a complete implementation of the BLAS interface adapted to asymmetric ARM big.LITTLE processors, analyzing the trade-offs between performance and energy efficiency when compared to existing homogeneous (symmetric) multi-threaded BLAS implementations. Our experimental results reveal important gains in performance while maintaining the energy efficiency of homogeneous solutions by efficiently exploiting all the resources of the asymmetric processor.