Scaling Monte Carlo Tree Search on Intel Xeon Phi

TL;DR

This paper investigates the parallelization and scaling of Monte Carlo Tree Search on Intel Xeon Phi hardware, demonstrating a high-performance implementation with effective thread management and scheduling strategies.

Contribution

It introduces a Grain Size Controlled Parallel MCTS approach and compares different threading models, achieving the fastest known implementation on Xeon Phi for real-world applications.

Findings

Work-sharing FIFO scheduling outperforms work-stealing approaches.

Controlling grain size is crucial for high parallel MCTS performance.

Achieved 47x speedup over sequential execution.

Abstract

Many algorithms have been parallelized successfully on the Intel Xeon Phi coprocessor, especially those with regular, balanced, and predictable data access patterns and instruction flows. Irregular and unbalanced algorithms are harder to parallelize efficiently. They are, for instance, present in artificial intelligence search algorithms such as Monte Carlo Tree Search (MCTS). In this paper we study the scaling behavior of MCTS, on a highly optimized real-world application, on real hardware. The Intel Xeon Phi allows shared memory scaling studies up to 61 cores and 244 hardware threads. We compare work-stealing (Cilk Plus and TBB) and work-sharing (FIFO scheduling) approaches. Interestingly, we find that a straightforward thread pool with a work-sharing FIFO queue shows the best performance. A crucial element for this high performance is the controlling of the grain size, an approach that we call Grain Size Controlled Parallel MCTS. Our subsequent comparing with the Xeon CPUs shows an even more comprehensible distinction in performance between different threading libraries. We achieve, to the best of our knowledge, the fastest implementation of a parallel MCTS on the 61 core Intel Xeon Phi using a real application (47 relative to a sequential run).