Computational Capacity and Energy Consumption of Complex Resistive Switch Networks

TL;DR

This paper models and simulates complex resistive switch networks, analyzing their computational capacity and energy consumption, and proposes a modular approach to optimize the trade-off for neuromorphic computing architectures.

Contribution

It introduces a detailed simulation framework linking physical parameters to computational capacity and energy use, and proposes a modular network design for improved efficiency.

Findings

Increasing network connectivity and switching activity boosts computational capacity linearly.

Energy consumption grows exponentially with capacity when increasing network activity.

A modular approach achieves higher capacity with linear energy growth.

Abstract

Resistive switches are a class of emerging nanoelectronics devices that exhibit a wide variety of switching characteristics closely resembling behaviors of biological synapses. Assembled into random networks, such resistive switches produce emerging behaviors far more complex than that of individual devices. This was previously demonstrated in simulations that exploit information processing within these random networks to solve tasks that require nonlinear computation as well as memory. Physical assemblies of such networks manifest complex spatial structures and basic processing capabilities often related to biologically-inspired computing. We model and simulate random resistive switch networks and analyze their computational capacities. We provide a detailed discussion of the relevant design parameters and establish the link to the physical assemblies by relating the modeling parameters to physical parameters. More globally connected networks and an increased network switching activity are means to increase the computational capacity linearly at the expense of exponentially growing energy consumption. We discuss a new modular approach that exhibits higher computational capacities and energy consumption growing linearly with the number of networks used. The results show how to optimize the trade-off between computational capacity and energy efficiency and are relevant for the design and fabrication of novel computing architectures that harness random assemblies of emerging nanodevices.